The SDR Blog

USRP1

• power: 6VDC, 3.5A
• interface: one Cypress FX2 USB 2.0, capable of 32 MByte/sec
• FPGA: one Altera Cyclone EP1C12
• internal clock: 64MHz
• AD/DA: two Analog Devices AD9862, each with two 12-bit 64-MSPS ADC and two 14-bit 128-MSPS DAC

USRP2

• power: same as USRP1
• interface: one Gigabit Ethernet, capable of 50 MHz of RF bandwidth #FIXME
• interface: 2 Gbps serial interface for expansion
• FPGA: one Xilinx Spartan-3 XC3S2000, includes 32-bit RISC softprocessor
• internal clock: 100 MHz
• memory: 1MByte on-board SRAM
• AD/DA: two 100 MS/s 14-bit ADC and two 400 MS/s 16-bit DAC
• storage: SD Card reader

Daughterboards

GnuRadio

• The processing blocks are written in C++
• The programs create flowgraphs (a top block and 0 or more hierarchical blocks) using Python
• The interface between C++ and Python is SWIG
• It is heavily oriented towards streaming data, but a message block for packet data is being developed
• It runs mainly on x86 CPUs, but a port to the Cell processor is under way
• A multi-core scheduler was included in v3.1.3 (23/08/2008)
• QWT is used for the GUI
• It makes heavy use of the libboost